Go to the Processor Forum, now!

Anyone working on SOC development needs to know about the latest advances in processor technology and design. The place to get a concentrated dose of processor education is the upcoming Spring Processor Forum, held in San Jose at the Doubletree Hotel this year on May 16-19. Go sign up. Tell 'em Steve sent you.

Wim Roelandts: ASICs will never die

For a good interview with Wim Roelandts, CEO of Xilinx, check out this article written by Ed Sperling at Electronic News. Instead of the usual FPGA bravado about taking over the world, Roelandts gives a very realistic picture of the FPGA versus ASIC design decision process as well as a good summary of Moore's Law and its immediate future.

The humbling elegance of butterfly navigation

Two scientists at the University of Massachusetts Medical School have discovered how Monarch butterflies navigate over thousands of miles between the US and Mexico during their annual migrations. The butterfly's eyes contain photoreceptors that are tuned to receive polarized UV light from the sun. These receptors are directly linked via neural fibers to a region of the butterfly's brain called the dorsolateral protocerebrum, which contains a circadian clock that controls the butterfly's metabolic cycles. By neurally combining the time of day and the incident angle of UV light from the sun, the Monarch's brain computes a compass heading in real time.

The next time you think you've designed a really "hot," complex embedded system, consider how difficult it still is for human designers to develop something as elegant and complex as the Monarch's migratory navigation system. Also, consider how you'd power such a system on fruit nectar and water.

More advice on designing multiprocessor SOCs

Earlier today, I wrote up Jack Ganssle's article on the software aspects and advantages of multiprocessor SOC design. TI Principal Fellow Gene Frantz has written up some good guidelines on how to develop multiprocessor SOCs in EE Times. Worth a look.

Build complex SOCs faster and cheaper

I've written before about the great articles authored by my good friend Jack Ganssle. He's a very popular engineer/writer with a better handle on embedded software issues than anyone else in the business. His latest article in Embedded Software Programmaing magazine, Subtract Software Costs by Adding CPUs, provides real meat in the form of quantitative substantiation to a gut feel that I've had for a while. Specifically, Ganssle's numbers show that you can get a system-level project out the door a lot faster by chopping the software into manageable pieces and assigning the pieces to a number of independent, intercommunicating processors.

There are many advantages to this approach. First, each piece of software can be written by a much smaller design team with much less communications overhead between team members. Second, you don't need one monster processor running at multiple gigahertz to execute all the code. Several smaller, slower processors can do the job in a less costly IC fab process and at much lower power. And third, this approach seems to cut the bug rate on embedded code.