Red Herring Profiles Tensilica, Inc.
Here at Tensilica, we’re thrilled that a publication as prestigious as The Red Herring chose to profile our company and CEO Chris Rowen in its March 21 issue. The 1-page article (plus a second page with a really big photo of Chris) does what it can to convey the arcane world of configurable, extensible processors and SOC design with limited space and much to say about the business of chip development in the 21st century. In the name of journalistic integrity and balance, the article quotes people who work at a couple of Tensilica’s competitors.
Unfortunately, our competition understandably doesn’t share the Herring’s journalistic sense of fair play and they used the opportunity to take some cheap shots. Imagine! Although Tensilica would never officially address the shortcomings of the competitors quoted by The Red Herring, through the wonder of the blogosphere and my personal blog it’s now a lot easier for me to return those underhanded volleys.
The Red Herring article quotes MIPS’ director of product strategy Tom Peterson. I’ve been on conference panels with Tom in the past and he’s a wily (as in cartoon character Wile E. Coyote) marketer. I really respect Tom’s ability to sling FUD; I think he’s one of the best. In the article, Tom is quoted as saying that “configurable cores are not as good a fit for products that run lots of software.” Now that’s just silly. The MIPS processors that Tom’s trying to flog are 32-bit RISC processors that can’t be configured.
Tensilica’s Xtensa processor cores are also 32-bit RISC processors. They can do everything a MIPS processor can do except run crusty old code compiled specifically for MIPS processors that can’t be updated because the original programmers have left or died off. Xtensa processors can also be configured so that they run specific target code faster…a lot faster. However, configuring and extending an Xtensa processor core doesn’t impair its ability to run any sort of software, but that’s just the impression Mr. Peterson would like to leave while he valiantly tries to distract the reader from realizing that MIPS cores are just too slow for most of the heavy lifting on today’s SOCs. Tom’s truly a wily guy. It’s too bad his processors are so big and slow.
Then the Herring article weighs in with a quote from Carl Schlachte, ARC International’s fifth CEO in four years. However, Mr. Schlachte’s approach to discussing the world of configurable processor cores closely resembles his many predecessor’s—he wraps a lie inside a truth sort of the way Tootsie Roll hides a soft chewy center inside a hard candy lollipop. Schlachte’s quote is: “We have been at this the longest. We can do it better than those guys.” It’s true that ARC’s had a configurable core longer than anyone. They developed a simple configurable processor core back when the company was called Argonaut Software, a video-game developer. That core was useful for developing new video games but the configuration tools were clearly never meant to be used outside of the company. Except for a few configuration options, any application-specific extensions made to an ARC core must be built by hand and manually verified.
Being first doesn’t mean being best. Tensilica has elevated automatic processor core extension to a fine art, especially with last year’s introduction of the XPRES Compiler, which automatically analyzes C or C++ code and then generates optimized processor extensions to accelerate the execution of that target code.
If you look at where Tensilica’s processors are being used in products today, you’ll see the target applications all require significant data processing: image and video compression/decompression, audio processing, and network packet processing. The Xtensa processor also runs operating systems and has displaced MIPS processors in that role. SOC developers see the Tensilica approach as a very fast way to develop the high-performance processing blocks they need for their SOC designs. On average, Tensilica’s customers put six processor cores on each of their SOC designs and some put a lot more (like a couple hundred). Tensilica isn’t so much competing with ARM, MIPS, or ARC as it is fundamentally changing the way SOCs are designed in the 21st century.
Unfortunately, our competition understandably doesn’t share the Herring’s journalistic sense of fair play and they used the opportunity to take some cheap shots. Imagine! Although Tensilica would never officially address the shortcomings of the competitors quoted by The Red Herring, through the wonder of the blogosphere and my personal blog it’s now a lot easier for me to return those underhanded volleys.
The Red Herring article quotes MIPS’ director of product strategy Tom Peterson. I’ve been on conference panels with Tom in the past and he’s a wily (as in cartoon character Wile E. Coyote) marketer. I really respect Tom’s ability to sling FUD; I think he’s one of the best. In the article, Tom is quoted as saying that “configurable cores are not as good a fit for products that run lots of software.” Now that’s just silly. The MIPS processors that Tom’s trying to flog are 32-bit RISC processors that can’t be configured.
Tensilica’s Xtensa processor cores are also 32-bit RISC processors. They can do everything a MIPS processor can do except run crusty old code compiled specifically for MIPS processors that can’t be updated because the original programmers have left or died off. Xtensa processors can also be configured so that they run specific target code faster…a lot faster. However, configuring and extending an Xtensa processor core doesn’t impair its ability to run any sort of software, but that’s just the impression Mr. Peterson would like to leave while he valiantly tries to distract the reader from realizing that MIPS cores are just too slow for most of the heavy lifting on today’s SOCs. Tom’s truly a wily guy. It’s too bad his processors are so big and slow.
Then the Herring article weighs in with a quote from Carl Schlachte, ARC International’s fifth CEO in four years. However, Mr. Schlachte’s approach to discussing the world of configurable processor cores closely resembles his many predecessor’s—he wraps a lie inside a truth sort of the way Tootsie Roll hides a soft chewy center inside a hard candy lollipop. Schlachte’s quote is: “We have been at this the longest. We can do it better than those guys.” It’s true that ARC’s had a configurable core longer than anyone. They developed a simple configurable processor core back when the company was called Argonaut Software, a video-game developer. That core was useful for developing new video games but the configuration tools were clearly never meant to be used outside of the company. Except for a few configuration options, any application-specific extensions made to an ARC core must be built by hand and manually verified.
Being first doesn’t mean being best. Tensilica has elevated automatic processor core extension to a fine art, especially with last year’s introduction of the XPRES Compiler, which automatically analyzes C or C++ code and then generates optimized processor extensions to accelerate the execution of that target code.
If you look at where Tensilica’s processors are being used in products today, you’ll see the target applications all require significant data processing: image and video compression/decompression, audio processing, and network packet processing. The Xtensa processor also runs operating systems and has displaced MIPS processors in that role. SOC developers see the Tensilica approach as a very fast way to develop the high-performance processing blocks they need for their SOC designs. On average, Tensilica’s customers put six processor cores on each of their SOC designs and some put a lot more (like a couple hundred). Tensilica isn’t so much competing with ARM, MIPS, or ARC as it is fundamentally changing the way SOCs are designed in the 21st century.
posted by Steve Leibson at
8:36 AM
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