To infinity and beyond!
The title quote is from Buzz Lightyear but the topic of this post is David Lammer's cover article on 65nm process technology in the July 11 EE Times. The article is about the 2005 Symposium on VLSI Technology held in Kyoto, Japan last month. A few points in this excellent article caught my eye with respect to system design.
Point one: 65 nm technology buys you a cool 10 million transistors per square millimeter! An economical chip is around 100mm squared, which works out to one billion transistors on the chip. Even a cheap 5x5mm chip made with 65nm technology carries 250 million transistors. Hand-coding enough RTL to fill these chips will take, like, "To infinity and beyond!" You'd better get ready to find a more efficient way to design chips.
Point two: If you sniff at point one and say that leading-edge 65nm process technology is only for high-priced, cutting-edge products, read the statement from Mark Pinto, Chief Technology Officer at Applied Materials: "Demand from China is only going to grow—and 65nm is absolutely ideal for consumer chips aimed at growing markets."
Point three: Srini Raghvendra, Senior Director of Design For Manufacturing at Synopsys said: "Design productivity, measured in terms of gates per engineering workday, must improve fourfold at 65nm over the 130nm node." Do you have a plan to achieve that?
Point four: Process technology, especially at the 65nm node and future nodes, will no longer provide the automatic power reductions that "classical" Moore's-Law scaling has delivered for the past 40 years. "Addressing the problem requires architectural, system-level decisions." said Eric Filseth, a Cadence marketing manager.
Point five: Hardware/software codesign becomes more crucial at 65nm. "Teams must start on software creation at the same time that RTL design commences." according to Tohru Furuyama, general manager of R&D at Toshiba's SOC engineering center in Kawasaki, Japan.
Point 6: Mask costs for 65nm chips are estimated at $3 million. That's still small compared to the cost of designing a chip with as many as a billion transistors, but it's not an insignificant sum. You'd better have some good simulation models that will run your application code before you tape out a mask set.
Point 7: Process variations can occur across a single die at the 65nm node, which means that more functional chips can be out of spec. To weed these out, you will need more at-speed testing, which means more built-in self testing (BIST) because otherwise, you can count on leaving these chips on testers for an hour apiece. Do you have a plan to add BIST to your designs? You'd better.
All of these issues are addressed by processor-centric SOC design. If you haven't yet read Engineering the Complex SOC by Chris Rowen and Steve Leibson, this would be a good time to do so. We keep a nice writeup on the book on the Tensilica Web site if you need more information.
Point one: 65 nm technology buys you a cool 10 million transistors per square millimeter! An economical chip is around 100mm squared, which works out to one billion transistors on the chip. Even a cheap 5x5mm chip made with 65nm technology carries 250 million transistors. Hand-coding enough RTL to fill these chips will take, like, "To infinity and beyond!" You'd better get ready to find a more efficient way to design chips.
Point two: If you sniff at point one and say that leading-edge 65nm process technology is only for high-priced, cutting-edge products, read the statement from Mark Pinto, Chief Technology Officer at Applied Materials: "Demand from China is only going to grow—and 65nm is absolutely ideal for consumer chips aimed at growing markets."
Point three: Srini Raghvendra, Senior Director of Design For Manufacturing at Synopsys said: "Design productivity, measured in terms of gates per engineering workday, must improve fourfold at 65nm over the 130nm node." Do you have a plan to achieve that?
Point four: Process technology, especially at the 65nm node and future nodes, will no longer provide the automatic power reductions that "classical" Moore's-Law scaling has delivered for the past 40 years. "Addressing the problem requires architectural, system-level decisions." said Eric Filseth, a Cadence marketing manager.
Point five: Hardware/software codesign becomes more crucial at 65nm. "Teams must start on software creation at the same time that RTL design commences." according to Tohru Furuyama, general manager of R&D at Toshiba's SOC engineering center in Kawasaki, Japan.
Point 6: Mask costs for 65nm chips are estimated at $3 million. That's still small compared to the cost of designing a chip with as many as a billion transistors, but it's not an insignificant sum. You'd better have some good simulation models that will run your application code before you tape out a mask set.
Point 7: Process variations can occur across a single die at the 65nm node, which means that more functional chips can be out of spec. To weed these out, you will need more at-speed testing, which means more built-in self testing (BIST) because otherwise, you can count on leaving these chips on testers for an hour apiece. Do you have a plan to add BIST to your designs? You'd better.
All of these issues are addressed by processor-centric SOC design. If you haven't yet read Engineering the Complex SOC by Chris Rowen and Steve Leibson, this would be a good time to do so. We keep a nice writeup on the book on the Tensilica Web site if you need more information.
posted by Steve Leibson at
1:38 PM
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