Happy birthday to Moore’s Law

On its 40th birthday (tomorrow), Gordon Moore’s prediction about the increasing number of components that can be put on an integrated circuit is very much alive and well. However, it’s often cited corollaries relating to device speed and power dissipation, which are often confused with the law itself, are in big trouble. But I’ll leave that discussion for another time.

The August 19, 1965 issue of Electronics Magazine published the original article written by Gordon Moore, who was Director of Fairchild Semiconductor’s R&D laboratories at the time. Moore’s article titled “Cramming more components onto integrated circuits” predicted an exponential growth in the number of “components” (transistors, diodes, resistors, and capacitors) that would be built on an integrated circuit as semiconductor fabrication expertise grew. His initial observation was that the device-doubling time was 18 months, later refined to 2 years.

Incredibly, Moore synthesized this remarkably accurate, long-lived truism from very few data points. The integrated circuit had only been invented in late 1959, a little more than five years before Moore’s article appeared. By 1965, integrated-circuit fabrication technology had progressed only to the point where it could put 50 or 60 components on a chip. Moore conjured his doubling-trick projection using the five data points he had available. His law put the industry on a breakneck course that has lasted 45 years and will surely continue for at least another 10-15 years. However, the doubling time, now administered by the International Technology Roadmap for Semiconductors (ITRS), may be stretching out to three years as we approach the fundamental atomic limits of the materials. (Trace widths on today's most advanced ICs are now only a couple of dozen atoms wide and gate-oxide thicknesses are less than 10 atoms thick.)

Ten years after his first article appeared, Moore spoke about his law at the IEEE’s 1975 International Electron Devices Meeting (IEDM) and said that he saw “no present reason to expect a change in this trend.” However, over the years, there have been frequent predictions of the law’s demise.

For example, the industry was facing the transition from 3- and 2-micron lithographies to 1-micron technology in 1984. At that time, the fear was not that semiconductor fabrication technology would fail to keep pace. Rather, the issue was the IC designers’ ability to design such complex chips, which was falling behind the abilities of the manufacturing processes. Bob Kirk and Tom Daspit of American Microsystems published these paragraphs in their article “Making the Design Transition,” published in a 1984 issue of Semiconductor International magazine:

“The ability to design complex ‘one-micron design rule’ ICs is, in fact, a key in the semiconductor industry’s transition to using such processes effectively. … The capabilities of one micron technology will not be fully exploited until sufficiently powerful tools in these areas emerge.”

Remarkably similar to the situation the industry faces today with nanometer design rules, no? The 1984 article continues:

“Design engineers are, in fact, now beginning the transition from pencil-and-paper logic design to interactive design using engineering workstations. …

It should be noted that wider use of automated design aids is contingent on the acceptance of some reduction in the use of circuit area—known as area penalty. …

Automated tools generally waste some silicon area; they are not as area efficient as human designers.

While industry pressure exists to reduce area penalty, the sheer complexity of one-micron circuits dictates that some area be traded off in favor of completing designs in a timely way with automated tools. The pressure to reduce area penalty can be softened by trading off total design cost against the total manufacturing costs.”

So, the issues of moving IC hardware designers to higher abstraction levels and trading off silicon area for design complexity and cycle time have been with us for at least 20 years. Even 20 years ago, Moore’s-Law scaling was providing more components than could be accommodated by the design tools and methodologies in use. The same is true today even though designers have jumped several levels of abstraction from hand-drawn transistors, through schematic-drafting CAD systems, to HDLs and logic synthesis. Moore’s Law continues to keep the raw silicon capabilities ahead of our design abilities and will do so for at least another decade. After that, we will need to find another medium to work in because silicon will be worked out.