More on Moore
Yesterday, I wrote about Moore’s Law and its 40th birthday. Well, today’s the actual day of the anniversary of Moore’s article in Electronics magazine and many people, including Gordon Moore, thought things might not get as far as they have. As recently as 1995, 30 years after writing that first article predicting exponential device growth in semiconductors, Moore said:
“As we go below 0.2 micron, the SIA road map says 0.18 micron line widths is the right number, we must use radiation of a wavelength that is absorbed by almost everything. Assuming more or less conventional optics, problems with depth of field, surface planarity and resist technology are formidable, to say nothing of the requirement that overlay accuracy must improve as fast as resolution if we are to really take maximum advantage of the finer lines.”
Moore delivered these words in 1995 to the members of SPIE, the International Society for Optical Engineering. Not very optimistic for the creator of Moore’s Law—and Moore went even further in describing his chart for lithographic progress:
“My plot goes only to the 0.18 micron generation, because I have no faith that simple extrapolation beyond that relates to reality.”
Getting even more serious, Moore said:
“Beyond this is really terra incognita, taking the term from the old maps. I have no idea what will happen beyond 0.18 microns.
In fact, I still have trouble believing we are going to be comfortable at 0.18 microns using conventional optical systems. Beyond this level, I do not see any way that conventional optics carries us any further. Of course, some of us said this about the one micron level. This time however, I think there are fundamental materials issues that will force a different direction.”
It didn’t happen the way Moore expected. Today, 180nm lithography is middle-of-the-road stuff and no one considers it miraculous while quarter-micron (250nm) lithography is trailing-edge and .35-micron technology—still in production—is absolutely Neolithic. Actually, even 130nm lithography is quite manufacturable today although it took a lot of engineering magic and ingenuity to “make it so.”
Even 90nm integrated circuits are already in production. In fact, the FPGA industry currently uses 90nm fabrication as its top-of-the-line technology foundation and 65nm chips are being fabricated, although no one would say that 65nm chips are yet in volume production. However, 65nm production in volume is clearly coming, of that there is no doubt. A couple of weeks ago, an article written by David Lammers in EE Times quoted Ted Vucuverich, senior vice president of advanced R&D at Cadence, as saying that the jump from 90nm to 65nm design rules might be quick indeed because the transition requires no change to the materials flow used in the current 90nm fabrication process so designers get the immense transistor bounty of the next design node without much of the pain normally associated with such a change.
Writing as a Regional Editor for EDN Magazine—way, way back in 1988—I described what was then the world’s smallest transistor: IBM had fabricated a transistor using 70nm design rules, which was an amazing feat in the disco decade. That 70nm transistor ran on 1V when nearly all digital ICs ran on 5V way back in 1988. Although the 70nm transistor required liquid-nitrogen cooling to combat thermal noise, the IBM researchers saw no fundamental reason why such tiny FETs couldn’t run at room temperature. Today we know they can. Quite well in fact. Back in 1989, leading-edge IC production technology used 0.7- or 0.8-micron (700 to 800nm) design rules. That was 10x what IBM had achieved in 1988 with its 70nm design rules and we are just starting to put such small transistors into production, some 17 years later.
So what is the smallest transistor made today? Just how far has Moore’s Law been stretched this early in the 21st century? In late 2003, NEC announced that it had built an FET with a 5nm gate length. Intel and AMD have publicly discussed fabrication of transistors with 10nm gate lengths and IBM built one with a 6nm gate length in 2002. (Note: For you purists, I know I’m mixing gate lengths and drawn geometries here for brevity’s sake. At the IEDM conference in 2002, AMD also discussed a flash memory that it built in conjunction with Stanford University using 5nm drawn geometries.)
These geometries are approximately 10x smaller than what’s used in today’s most advanced production devices. So, we already know that transistors will continue to work at geometries an order of magnitude smaller than what’s broadly manufacturable today and we already know ways to make such transistors. The ability to make such small transistors in production volumes will undoubtedly follow because the economic incentives to make things smaller and cheaper remain.
Even after 40 years, it looks like Moore’s Law still has a few birthdays left.
PS: How Moore’s Law got its name
Gordon Moore isn’t really the sort of guy to name a law after himself. He had help. Rick Merritt and Patrick Mannion told the story in an article in this week’s EE Times. It seems that it took another huge name in semiconductor lore, Carver Mead, to bestow the name. Mead started consulting for Moore back in Moore’s days at Fairchild and continued after Moore co-founded Intel. Mead named the law in an interview with a journalist in 1971. Mead was discussing his work on electron tunneling and the associated limits on device scalability. He spontaneously coined the catchy phrase during the interview. The rest is well-trodden history.
“As we go below 0.2 micron, the SIA road map says 0.18 micron line widths is the right number, we must use radiation of a wavelength that is absorbed by almost everything. Assuming more or less conventional optics, problems with depth of field, surface planarity and resist technology are formidable, to say nothing of the requirement that overlay accuracy must improve as fast as resolution if we are to really take maximum advantage of the finer lines.”
Moore delivered these words in 1995 to the members of SPIE, the International Society for Optical Engineering. Not very optimistic for the creator of Moore’s Law—and Moore went even further in describing his chart for lithographic progress:
“My plot goes only to the 0.18 micron generation, because I have no faith that simple extrapolation beyond that relates to reality.”
Getting even more serious, Moore said:
“Beyond this is really terra incognita, taking the term from the old maps. I have no idea what will happen beyond 0.18 microns.
In fact, I still have trouble believing we are going to be comfortable at 0.18 microns using conventional optical systems. Beyond this level, I do not see any way that conventional optics carries us any further. Of course, some of us said this about the one micron level. This time however, I think there are fundamental materials issues that will force a different direction.”
It didn’t happen the way Moore expected. Today, 180nm lithography is middle-of-the-road stuff and no one considers it miraculous while quarter-micron (250nm) lithography is trailing-edge and .35-micron technology—still in production—is absolutely Neolithic. Actually, even 130nm lithography is quite manufacturable today although it took a lot of engineering magic and ingenuity to “make it so.”
Even 90nm integrated circuits are already in production. In fact, the FPGA industry currently uses 90nm fabrication as its top-of-the-line technology foundation and 65nm chips are being fabricated, although no one would say that 65nm chips are yet in volume production. However, 65nm production in volume is clearly coming, of that there is no doubt. A couple of weeks ago, an article written by David Lammers in EE Times quoted Ted Vucuverich, senior vice president of advanced R&D at Cadence, as saying that the jump from 90nm to 65nm design rules might be quick indeed because the transition requires no change to the materials flow used in the current 90nm fabrication process so designers get the immense transistor bounty of the next design node without much of the pain normally associated with such a change.
Writing as a Regional Editor for EDN Magazine—way, way back in 1988—I described what was then the world’s smallest transistor: IBM had fabricated a transistor using 70nm design rules, which was an amazing feat in the disco decade. That 70nm transistor ran on 1V when nearly all digital ICs ran on 5V way back in 1988. Although the 70nm transistor required liquid-nitrogen cooling to combat thermal noise, the IBM researchers saw no fundamental reason why such tiny FETs couldn’t run at room temperature. Today we know they can. Quite well in fact. Back in 1989, leading-edge IC production technology used 0.7- or 0.8-micron (700 to 800nm) design rules. That was 10x what IBM had achieved in 1988 with its 70nm design rules and we are just starting to put such small transistors into production, some 17 years later.
So what is the smallest transistor made today? Just how far has Moore’s Law been stretched this early in the 21st century? In late 2003, NEC announced that it had built an FET with a 5nm gate length. Intel and AMD have publicly discussed fabrication of transistors with 10nm gate lengths and IBM built one with a 6nm gate length in 2002. (Note: For you purists, I know I’m mixing gate lengths and drawn geometries here for brevity’s sake. At the IEDM conference in 2002, AMD also discussed a flash memory that it built in conjunction with Stanford University using 5nm drawn geometries.)
These geometries are approximately 10x smaller than what’s used in today’s most advanced production devices. So, we already know that transistors will continue to work at geometries an order of magnitude smaller than what’s broadly manufacturable today and we already know ways to make such transistors. The ability to make such small transistors in production volumes will undoubtedly follow because the economic incentives to make things smaller and cheaper remain.
Even after 40 years, it looks like Moore’s Law still has a few birthdays left.
PS: How Moore’s Law got its name
Gordon Moore isn’t really the sort of guy to name a law after himself. He had help. Rick Merritt and Patrick Mannion told the story in an article in this week’s EE Times. It seems that it took another huge name in semiconductor lore, Carver Mead, to bestow the name. Mead started consulting for Moore back in Moore’s days at Fairchild and continued after Moore co-founded Intel. Mead named the law in an interview with a journalist in 1971. Mead was discussing his work on electron tunneling and the associated limits on device scalability. He spontaneously coined the catchy phrase during the interview. The rest is well-trodden history.
posted by Steve Leibson at
9:30 AM
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